CLB

CLB R[x], R[y],b - Clear Bit

Operating Mode

R[x] := R[y]15R[y]14...R[y]b+1 0 R[y]b-1........R[y]0

PC := PC + 1

Description

Takes register R[y], clears Bit at position b and saves result to register R[x].

Status Register

Zero - Bit := 1 if all Bits of R[y] are 0 after operation

Binary Command

15 14 13 12 11	10 9 8	7	6	5 4 3	2 1 0
10011	Adr(x)	-	b3	Adr(y)	b2 b1 b0

Example

CLB R[5], R[2],13

15 14 13 12 11	10 9 8	7	6	5 4 3	2 1 0
10011	101	-	1	010	101

Note
Arithmetic and Logical Commands always affect the Status Bits Carry and Zero.
After any Logical Command the Carry Bit is set to 0.